Datasheet

Section 22 Synchronous Serial Communication Unit (SSU)
Page 778 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
22.2.7 SS Status Register (SSSR)
Address:
Bit:
Value after reset:
b7
TDRE
0
b6
TEND
0
b5
RDRF
0
b4
⎯
0
b3
⎯
0
b2
ORER
0
b1
⎯
0
b0
CE
0
H'FF05CC
Bit Symbol Bit Name Description R/W
7 TDRE Transmit data
empty flag
[Setting conditions]
• When the TE bit in SSER is 0
• When data transfer is performed from SSTDR to
SSTRSR and data can be written in SSTDR
[Clearing conditions]
• When 0 is written to this bit after reading 1
• When data is written in SSTDR
• When the DTC transfers data to SSTDR by a
TXI interrupt request, and the DTC settings
satisfy the flag clearing conditions.*
R/W
6 TEND Transmit end
flag
[Setting condition]
• When the last bit of data is transmitted, the
TDRE bit is 1
[Clearing conditions]
• When 0 is written to this bit after reading 1
• When data is written in SSTDR
R/W
5 RDRF Receive data
register full flag
[Setting condition]
• When serial reception is completed normally
and receive data is transferred from SSTRSR to
SSRDR
[Clearing conditions]
• When 0 is written to this bit after reading 1
• When data is read from SSRDR
• When the DTC transfers data to SSRDR by an
RXI interrupt request, and the DTC settings
satisfy the flag clearing conditions.*
R/W