Datasheet

Section 22 Synchronous Serial Communication Unit (SSU)
REJ09B0465-0300 Rev. 3.00 Page 777 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
22.2.6 SS Enable Register (SSER)
Address:
Bit:
Value after reset:
b7
TIE
0
b6
TEIE
0
b5
RIE
0
b4
TE
0
b3
RE
0
b2
⎯
0
b1
⎯
0
b0
CEIE
0
H'FF05CB
Bit Symbol Bit Name Description R/W
7 TIE Transmit interrupt
enable
0: A TXI interrupt request is disabled.
1: A TXI interrupt request is enabled.
R/W
6 TEIE Transmit end
interrupt enable
0: A TEI interrupt request is disabled.
1: A TEI interrupt request is enabled.
R/W
5 RIE Receive interrupt
enable
0: An RXI and an OEI interrupt requests are disabled.
1: An RXI and an OEI interrupt requests are enabled.
R/W
4 TE* Transmit enable 0: Transmit operation is disabled.
1: Transmit operation is enabled.
R/W
3 RE* Receive enable 0: Receive operation is disabled.
1: Receive operation is enabled.
R/W
2, 1 ⎯ Reserved These bits are read as 0. The write value should be 0. ⎯
0 CEIE Conflict error
interrupt enable
0: A CEI interrupt request is disabled.
1: A CEI interrupt request is enabled.
R/W
Note: * The TE and RE bits are reset in standby mode.