Datasheet

Section 22 Synchronous Serial Communication Unit (SSU)
Page 770 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
22.2.2 SS Control Register H (SSCRH)
Address:
Bit:
Value after reset:
b7
⎯
0
b6
RSSTP
0
b5
MSB
0
b4
⎯
0
b3
⎯
0
b2
0
b1
CKS[2:0]
0
b0
0
H'FF05C8
Bit Symbol Bit Name Description R/W
7 ⎯ Reserved This bit is read as 0. The write value should be 0. ⎯
6 RSSTP Receive single
stop
0: After receiving 1 byte of data, reception continues.
1: After receiving 1 byte of data, reception ends.*
R/W
5 MSS Master/slave
device select
0: Operates as a slave device
1: Operates as a master device
R/W
4, 3 ⎯ Reserved These bits are read as 0. The write value should be 0. ⎯
2 to 0 CKS[2:0] Transfer clock
rate select
000: φ/256
001: φ/128
010: φ/64
011: φ/32
100: φ/16
101: φ/8
110: φ/4
111: Reserved
R/W
Note: * The setting of the RSSTP bit is invalid when the MSS bit is cleared to 0.
• MSS bit (master/slave device select)
Selects whether this module is used as a master device or a slave device. When this module is
used as a master device, transfer clock is output from the SSCK pin. When the CE bit in SSSR
is set, this bit is automatically cleared.
• CKS[2:0] bits (transfer clock rate select)
Sets transfer clock rate (prescaler division ratio) when the internal clock is selected.