Datasheet

Section 22 Synchronous Serial Communication Unit (SSU)
Page 768 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
SSMR
SSCRL
SSCRH
SSER
SSSR
SSTDR
Internal data bus
SSO
SCS
SSCK
Multiplexer
Transmission/
reception
control circuit
Internal clock
SSI
SSTRSR
SSRDR
Interrupt request
(TXI, TEI, RXI, OEI, CEI)
SSMR2
Selector
Figure 22.1 Block Diagram of SSU
Table 22.1 shows the pin configuration of the SSU.
Table 22.1 Pin Configuration
Pin Name I/O Function
SSCK I/O SSU clock input/output
SSI I/O SSU data input/output
SSO I/O SSU data input/output
SCS I/O SSU chip select input/output