Datasheet

Section 22 Synchronous Serial Communication Unit (SSU)
REJ09B0465-0300 Rev. 3.00 Page 767 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Section 22 Synchronous Serial Communication Unit (SSU)
Note: In this section, the synchronous serial communication unit is abbreviated as SSU for
convenience.
The synchronous serial communication unit (SSU) can handle clocked synchronous serial data
communication.
Figure 22.1 shows a block diagram of the SSU.
Either the SSU or IIC2 incorporated in this LSI can be used at a time. Accordingly, when the SSU
function is used, the IIC2 function is not available.
22.1 Features
• Can be operated in clocked synchronous communication mode or four-line bus communication
mode (including bidirectional communication mode)
• Can be operated as a master or a slave device
• Choice of seven internal clocks (φ/256, φ/128, φ/64, φ/32, φ/16, φ/8, φ/4) and an external clock
as a clock source
• Clock polarity and phase of SSCK can be selected
• Choice of data transfer direction (MSB-first or LSB-first)
• Receive error detection: overrun error
• Multimaster error detection: conflict error
• Five interrupt sources: transmit-end, transmit-data-empty, receive-data-full, overrun error, and
conflict error. The DTC can be activated by the transmit-data-empty and receive-data-full
interrupts.
• The transmitter and receiver with buffer structure allow continuous transmission and reception
of serial data.