Datasheet

Section 21 I

C Bus Interface 2 (IIC2)

Page 766 of 982 REJ09B0465-0300 Rev. 3.00

Sep 17, 2010

H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group

21.6.4 Note on Access to ICE in ICCR1 and IICRST in ICCR2 during I

C Bus Operation

Writing 0 to ICE in ICCR1 or 1 to IICRST in ICCR2 while any of the following four conditions

during I

C bus operation is satisfied leads to undefined values for BBSY in ICCR2 and STOP in

ICSR.

1. This module holds the I

C bus mastership and is in master transmit mode (MST = 1 and TRS =

1 in ICCR1)

2. This module holds the I

C bus mastership and is in master receive mode (MST = 1 and TRS =

0 in ICCR1)

3. This module is transmitting data in slave transmit mode (MST = 0 and TRS = 1 in ICCR1).

4. This module is transmitting an acknowledge signal in slave receive mode (MST = 0 and TRS =

0 in ICCR1).

Use any of the following workarounds to resolve the undefined state of BBSY in ICCR2.

• Input a start condition (falling edge of SDA while SCL is at the high level) so that BBSY is set

to 1.

• Input a stop condition (rising edge of SDA while SCL is at the high level) so that BBSY is

cleared to 0.

• In master transmit mode, write 1 to BBSY and 0 to SCP in ICCR2 while SCL and SDA are

both at the high level to generate a start condition. BBSY is set to 1 when the start condition

(falling edge of SDA while SCL is at the high level) is output.

• In master transmit mode or master receive mode, when SDA is at the low level and there is no

device other than this module to drive SCL low, write 0 to BBSY and SCP in ICCR2 to

generate a stop condition. BBSY is cleared to 0 when the stop condition (rising edge of SDA

while SCL is at the high level) is output.

• Writing 1 to FS in SAR causes BBSY to be cleared to 0.