Datasheet

Section 21 I

C Bus Interface 2 (IIC2)

Page 764 of 982 REJ09B0465-0300 Rev. 3.00

Sep 17, 2010

H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group

21.5 Bit Synchronous Circuit

In master mode, this module has a possibility that high level period may be shortened in the two

states described below.

• When SCL is driven to low by the slave device

• When the rising speed of SCL is lowered by the load of the SCL line (load capacitance or pull-

up resistance)

Therefore, it monitors SCL and communicates by bit with synchronization.

Figure 21.21 shows the timing of the bit synchronous circuit and table 21.4 shows the time when

SCL output changes from low to Hi-Z and then SCL is monitored.

SCL

VIH

SCL monitor

timing reference

clock

Internal SCL

Figure 21.21 The Timing of the Bit Synchronous Circuit

Table 21.4 Time for Monitoring SCL

CKS3 CKS2 Time for Monitoring SCL

0 0 7.5 tcyc

1 19.5 tcyc

1 0 17.5 tcyc

1 41.5 tcyc