Datasheet

Section 21 I
2
C Bus Interface 2 (IIC2)
REJ09B0465-0300 Rev. 3.00 Page 757 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
(3) Receive Operation
In receive mode, data is latched at the rise of the transfer clock. The transfer clock is output when
MST in ICCR1 is 1 and is input when MST is 0. For receive mode operation timing, see figure
21.15. The reception procedure and operations in receive mode are described below.
1. Set the ICE bit in ICCR1 to 1. Set the MST and CKS3 to CKS0 bits in ICCR1 to 1 (Initial
setting).
2. When the transfer clock is output, set MST to 1 to start outputting the receive clock.
3. When the receive operation is completed, data is transferred from ICDRS to ICDRR and
RDRF in ICSR is set. When MST = 1, the next byte can be received, so the clock is
continually output. The continuous reception is performed by reading ICDRR every time
RDRF is set. When the 8th clock is risen while RDRF is set to 1, the overrun is detected and
AL/OVE in ICSR is set. At this time, the previous reception data is retained in ICDRR.
4. To stop receiving when MST = 1, read ICDRR after setting RCVD in ICCR1 to 1. Then, SCL
is fixed high after receiving the next byte data.
12 781 7812
SCL
MST
TRS
RDRF
ICDRS
ICDRR
SDA
(Input)
Bit 0
Bit 6 Bit 7 Bit 0 Bit 6 Bit 7 Bit 0 Bit 1
Bit 1
User
processing
Data 1
Data 1
Data 2
Data 2
Data 3
[2] Set MST
(when outputting the clock)
[3] Read ICDRR [3] Read ICDRR
Figure 21.15 Receive Mode Operation Timing