Datasheet

Section 21 I
2
C Bus Interface 2 (IIC2)
Page 748 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
7. When the STOP bit in ICSR is set to 1, the operation returns to the slave receive mode.
TDRE
SCL
(Master output)
SDA
(Master output)
SDA
(Slave output)
TEND
[5] Write data to ICDRT (third byte)
ICDRT
ICDRS
[2] Instruction of start
condition issuance
[3] Write data to ICDRT (first byte)
[4] Write data to ICDRT (second byte)
User
processing
1
Bit 7
Slave address
Address + R/W
Data 1
Data 1
Data 2
Address + R/W
Bit 6 Bit 7 Bit 6Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
2123456789
A
R/W
Figure 21.5 Master Transmit Mode Operation Timing (1)
TDRE
[6] Issue stop condition. Clear TEND.
[7] Set slave receive mode
TEND
ICDRT
ICDRS
19 23456789
A
A/A
SCL
(Master output)
SDA
(Master output)
SDA
(Slave output)
Bit 7 Bit 6
Data n
Data n
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
[5] Write data to ICDRT
User
processing
Figure 21.6 Master Transmit Mode Operation Timing (2)