Datasheet

Section 21 I

C Bus Interface 2 (IIC2)

REJ09B0465-0300 Rev. 3.00 Page 745 of 982

Sep 17, 2010

H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group

21.2.8 I

C Bus Transmit Data Register (ICDRT)

Address:

Bit:

Value after reset:

H'FF05CE

ICDRT is an 8-bit readable/writable register that stores the transmit data. When ICDRT detects the

space in the shift register (ICDRS), it transfers the transmit data which is written in ICDRT to

ICDRS and starts transferring data. If the next transfer data is written to ICDRT during

transferring data of ICDRS, continuous transfer is possible. If the MLS bit of ICMR is set to 1 and

when the data is written to ICDRT, the MSB/LSB inverted data is read. The initial value of

ICDRT is H'FF. ICDRT is reset in standby mode.

21.2.9 I

C Bus Receive Data Register (ICDRR)

Address:

Bit:

Value after reset:

H'FF05CF

ICDRR is an 8-bit register that stores the receive data. When data of one byte is received, ICDRR

transfers the receive data from ICDRS to ICDRR and the next data can be received. ICDRR is a

receive-only register, therefore the CPU cannot write to this register. The initial value of ICDRR is

H'FF. ICDRR is reset in standby mode.

21.2.10 I

C Bus Shift Register (ICDRS)

Address:

Bit:

Value after reset:

⎯

ICDRS is a register that is used to transfer/receive data. In transmission, data is transferred from

ICDRT to ICDRS and the data is sent from the SDA pin. In reception, data is transferred from

ICDRS to ICDRR after data of one byte is received. This register cannot be read directly from the

CPU. ICDRS is reset in standby mode.