Datasheet

Section 21 I
2
C Bus Interface 2 (IIC2)
REJ09B0465-0300 Rev. 3.00 Page 743 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Bit Symbol Bit Name Description R/W
2 AL_OVE Arbitration lost
flag/overrun error
flag
[Setting conditions]
• If the internal SDA and SDA pin disagree at the
rise of SCL in master transmit mode
• When the SDA pin outputs high in master mode
while a start condition is detected
• When the final bit is received with the clock
synchronous format while RDRF = 1
[Clearing condition]
• When 0 is written in AL/OVE after reading
AL/OVE = 1
R/W
1 AAS Slave address
recognition flag
[Setting conditions]
• When the slave address is detected in slave
receive mode
• When the general call address is detected in
slave receive mode.
[Clearing condition]
• When 0 is written in AAS after reading AAS = 1
R/W
0 ADZ General call
address
recognition flag
This bit is enabled in slave receive mode with I
2
C bus
format.
[Setting condition]
• When the general call address is detected in
slave receive mode
[Clearing condition]
• When 0 is written in ADZ after reading ADZ = 1
R/W
Notes: In standby mode, ICSR is reset.
* The DTC clears the peripheral module flags when all of the following three conditions
are satisfied.
1. When the DISEL bit is 0.
2. When the transfer counter is not 0. (DTC transfer count register A (CRA) in normal
mode and repeat mode, or DTC transfer count register B (CRB) in block mode)
3. When chain transfer is not used.