Datasheet

Section 21 I
2
C Bus Interface 2 (IIC2)
Page 738 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
• WAIT bit (wait insertion)
In master mode with the I
2
C bus format, this bit selects whether to insert a wait after data
transfer except the acknowledge bit. When WAIT is set to 1, after the fall of the clock for the
final data bit, low period is extended for two transfer clocks. If WAIT is cleared to 0, data and
acknowledge bits are transferred consecutively with no wait inserted.
The setting of this bit is invalid in slave mode with the I
2
C bus format or with the clock
synchronous serial format.
• BCWP bit (BC write protect)
Controls the BC2 to BC0 modifications. When modifying BC2 to BC0, this bit should be
cleared to 0 and use the MOV instruction. In clock synchronous serial mode, BC should not be
modified.
• BC[2:0] bits (bit counter 2 to 0)
Specifies the number of bits to be transferred next. When read, the remaining number of
transfer bits is indicated. With the I
2
C bus format, the data is transferred with one additional
acknowledge bit. Bit BC2 to BC0 should be set during an interval between transfer frames. If
bits BC2 to BC0 are set to a value other than 000, the setting should be made while the SCL
pin is low. The value automatically returns to 000 at the end of a data transfer, including the
acknowledge bit. With the clock synchronous serial format, these bits should not be modified.