Datasheet

Section 21 I
2
C Bus Interface 2 (IIC2)
REJ09B0465-0300 Rev. 3.00 Page 735 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
21.2.3 I
2
C Bus Control Register 2 (ICCR2)
Address:
Bit:
Value after reset:
b7
BBSY
0
b6
SCP
1
b5
SDAO
1
b4
SDAOP
1
b3
SCLO
1
b2
⎯
1
b1
IICRST
0
b0
⎯
1
H'FF05C9
Bit Symbol Bit Name Description R/W
7 BBSY*
1
*
3
Bus busy This bit enables to confirm whether the I
2
C bus is
occupied or released and to issue start/stop
conditions in master mode. With the clock
synchronous serial format, this bit has no meaning.
With the I
2
C bus format, this bit is set to 1 when the
SDA level changes from high to low under the
condition of SCL = high, assuming that the start
condition has been issued. This bit is cleared to 0
when the SDA level changes from low to high under
the condition of SCL = high, assuming that the stop
condition has been issued. Write 1 to BBSY and 0
to SCP to issue a start condition. Follow this
procedure when also re-transmitting a start
condition. Write 0 in BBSY and 0 in SCP to issue a
stop condition. To issue start/stop conditions, use
the MOV instruction.
R/W
6 SCP*
3
Start/stop
condition issue
disable
The SCP bit controls the issue of start/stop
conditions in master mode. To issue a start
condition, write 1 in BBSY and 0 in SCP. A
retransmit start condition is issued in the same way.
To issue a stop condition, write 0 in BBSY and 0 in
SCP. This bit is always read as 1. If 1 is written, the
data is not stored.
R/W
5 SDAO*
3
SDA output
value control
This bit is used with SDAOP (bit 4) when modifying
output level of SDA. This bit should not be
manipulated during transfer. Writing 1 to the IICRST
bit also sets this bit to 1.
0: When reading, SDA pin outputs low.
When writing, SDA pin is changed to output low.
1: When reading, SDA pin outputs high.
When writing, SDA pin is changed to output Hi-Z
(outputs high by external pull-up resistance).
R/W