Datasheet

Section 20 Serial Communication Interface 3 (SCI3, IrDA)
REJ09B0465-0300 Rev. 3.00 Page 727 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
20.9.5 Relation between Writes to TDR and TDRE Flag
Data can be written to TDR regardless of the state of the TDRE flag. However, if new data is
written to TDR when the TDRE flag is cleared to 0, the data stored in TDR will be lost since it has
not yet been transferred to TSR. It is therefore essential to check that the TDRE flag is set to 1
before writing transmit data TDR.
20.9.6 Restrictions on Using DTC
When the external clock source is used as a synchronization clock, update TDR by the DTC or
CPU and wait for at least five φ clock cycles before allowing the transmit clock to be input. If the
transmit clock is input within four clock cycles after TDR modification, the SCI3 may malfunction
(see figure 20.23).
When using the DTC to read RDR, be sure to set the receive end interrupt (RXI) for the relevant
SCI3 as the DTC activation source.
t
D0
LSB
Serial data
SCK3
D1 D3 D4 D5D2 D6 D7
Note: When an external clock is supplied, t must be more than four clock cycles.
TDRE
Figure 20.23 Example of DTC Transmission in Clock Synchronous Mode