Datasheet

Section 20 Serial Communication Interface 3 (SCI3, IrDA)
REJ09B0465-0300 Rev. 3.00 Page 725 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
20.9 Usage Notes
20.9.1 Break Detection and Processing
When framing error detection is performed, a break can be detected by reading the RXD pin value
directly. In a break, the input from the RXD pin becomes all 0s, setting the FER flag, and possibly
the PER flag. Note that as the SCI3 continues the receive operation after receiving a break, even if
the FER flag is cleared to 0, it will be set to 1 again.
20.9.2 Mark State and Break Sending
When the PMR bit corresponding to the pin selected by the PMC is 0, the TXD pin is used as an
I/O port whose direction (input or output) and level are determined by PCR and PDR. This can be
used to set the TXD pin to mark state (high level) or send a break during data transmission. To
maintain the communication line at mark state until the PMR bit is set to 1, set both PCR and PDR
to 1. As the PMR bit is cleared to 0 at this point, the TXD pin becomes an I/O port, and 1 is output
from the TXD pin. To send a break during transmission, first set PCR to 1 and clear PDR to 0, and
then clear the PMR bit to 0. When the PMR bit is cleared to 0, the transmitter is initialized
regardless of the current transmission state, the TXD pin becomes an I/O port, and 0 is output
from the TXD pin.
20.9.3 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)
Transmission cannot be started when a receive error flag (OER, PER, or FER) is set to 1, even if
the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting
transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared
to 0.