Datasheet

Section 20 Serial Communication Interface 3 (SCI3, IrDA)
REJ09B0465-0300 Rev. 3.00 Page 721 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
20.6.1 Transmission
During transmission, the output signals from the SCI3_2 (UART frames) are converted to IR
frames using the IrDA interface (see figure 20.20). For serial data of level 0, a high-level pulse
having a width of 3/16 of the bit rate (1-bit interval) is output (initial setting). The high-level pulse
can be selected using the IrCK2 to IrCK0 bits in IrCR. The high-level pulse width is defined to be
1.41 µs at minimum and (3/16 + 2.5%) × bit rate or (3/16 × bit rate) +1.08 µs at maximum. For
example, when the frequency of system clock φ is 20 MHz, a high-level pulse width of 1.6 µs can
be specified because it is the smallest value in the range greater than 1.41 µs. For serial data of
level 1, no pulses are output.
UART frame
Data
IR frame
Data
0000 011 111
0000 011 111
Start
bit
Transmission
Reception
Stop
bit
Start
bit
Stop
bit
Bit
cycle
Pulse width is 1.6 ms to
3/16 bit cycle.
Figure 20.20 IrDA Transmission and Reception
20.6.2 Reception
During reception, IR frames are converted to UART frames using the IrDA interface before
inputting to SCI3_2. 0 is output when the high level pulse is detected while 1 is output when no
pulse is detected during one bit period. Note that a pulse shorter than the minimum pulse width of
1.41 µs is regarded as a 0 signal.