Datasheet

Section 20 Serial Communication Interface 3 (SCI3, IrDA)
Page 716 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
20.5.2 Multiprocessor Data Reception
Figure 20.17 shows a sample flowchart for multiprocessor data reception. If the MPIE bit in SCR3
is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data with a 1
multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is generated at
this time. All other SCI3 operations are the same as those in asynchronous mode. Figure 20.18
shows an example of SCI3 operation for multiprocessor data reception.