Datasheet

Section 2 CPU
Page 48 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Table 2.6 Shift Instructions
Instruction Size
*
Function
SHAL
SHAR
B/W/L Rd (shift) → Rd
Performs an arithmetic shift on data in a general register. 1-bit or 2 bit
shift is possible.
SHLL
SHLR
B/W/L Rd (shift) → Rd
Performs a logical shift on data in a general register. 1-bit or 2 bit shift
is possible.
ROTL
ROTR
B/W/L Rd (rotate) → Rd
Rotates data in a general register. 1-bit or 2 bit rotation is possible.
ROTXL
ROTXR
B/W/L Rd (rotate) → Rd
Rotates data including the carry flag in a general register. 1-bit or 2 bit
rotation is possible.
Note: * Size refers to the operand size.
B: Byte
W: Word
L: Longword