Datasheet

Section 20 Serial Communication Interface 3 (SCI3, IrDA)
REJ09B0465-0300 Rev. 3.00 Page 689 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Bit Symbol Bit Name Description R/W
4 FER Framing error
flag
[Setting condition]
• When a framing error occurs in reception
[Clearing condition]
• When the CPU writes 0 after reading FER = 1.
R/W
3 PER Parity error
flag
[Setting condition]
• When a parity error is detected during reception
[Clearing condition]
• When the CPU writes 0 after reading PER = 1.
R/W
2 TEND Transmit end
flag
[Setting conditions]
• When the TE bit in SCR3 is 0
• When TDRE = 1 at transmission of the last bit of a
transmit character
[Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When the transmit data is written to TDR
R/W
1 MPBR Multiprocessor
bit receive
Stores the multiprocessor bit in the receive character data.
When the RE bit in SCR3 is cleared to 0, its state is
retained.
R/W
0 MPBT Multiprocessor
bit transfer
Specifies the multiprocessor bit value to be added to the
transmit character data.
R/W
Notes: * The DTC clears the peripheral module flags when all of the following three conditions
are satisfied:
1. The DISEL bit is 0.
2. The value in the transfer counter (count register CRA in normal and repeat modes or
count register CRB in block mode) is not 0.
3. A chain transfer is not used.