Datasheet

Section 20 Serial Communication Interface 3 (SCI3, IrDA)
Page 688 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
20.2.7 Serial Status Register (SSR)
Address:
Bit:
Value after reset:
b7
TDRE
1
b6
RDRF
0
b5
OER
0
b4
FER
0
b3
PER
0
b2
TEND
1
b1
MPBR
0
b0
MPBT
0
H'FF0554, H'FF055C, H'FF0564
Bit Symbol Bit Name Description R/W
7 TDRE Transmit
data register
empty flag
[Setting conditions]
When the TE bit in SCR3 is 0
When data is transferred from TDR to TSR
[Clearing conditions]
When the CPU writes 0 after reading TDRE = 1.
When the CPU writes transmit data to TDR.
When the DTC transfers data to TDR with a TXI interrupt
request and the DTC settings satisfy the flag clearing
conditions. *
R/W
6 RDRF Receive
data register
full flag
[Setting condition]
When reception ends normally and receive data is
transferred from RSR to RDR
[Clearing conditions]
When the CPU writes 0 after reading RDRF = 1.
When the CPU reads data from RDR.
When the DTC transfers data from RDR with an RXI
interrupt request and the DTC settings satisfy the flag
clearing conditions. *
R/W
5 OER Overrun
error flag
[Setting condition]
When an overrun error occurs in reception
[Clearing condition]
When the CPU writes 0 after reading OER = 1.
R/W