Datasheet

Section 20 Serial Communication Interface 3 (SCI3, IrDA)
Page 686 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
20.2.6 Serial Control Register 3 (SCR3)
Address:
Bit:
Value after reset:
b7
TIE
0
b6
RIE
0
b5
TE
0
b4
RE
0
b3
MPIE
0
b2
TEIE
0
b1
0
b0
0
H'FF0552, H'FF055A, H'FF0562
CKE[1:0]
Bit Symbol Bit Name Description R/W
7 TIE Transmit
interrupt enable
0: The TXI interrupt request is disabled.
1: The TXI interrupt request is enabled.
R/W
6 RIE Receive interrupt
enable
0: RXI and ERI interrupt requests are disabled.
1: RXI and ERI interrupt requests are enabled.
R/W
5 TE Transmit enable 0: Transmission is disabled.
1: Transmission is enabled.
R/W
4 RE Receive enable 0: Reception is disabled.
1: Reception is enabled.
R/W
3 MPIE Multiprocessor
interrupt enable
(Enabled only when the MP bit in SMR is 1 in
asynchronous mode)
When this bit is set to 1, receive data in which the
multiprocessor bit is 0 is skipped, and setting of the
RDRF, FER, and OER status flags in SSR is disabled.
On receiving data in which the multiprocessor bit is 1,
this bit is automatically cleared and normal reception is
resumed. For details, see section 20.5, Multiprocessor
Communication Function.
R/W
2 TEIE Transmit end
interrupt enable
0: The TEI interrupt request is disabled.
1: The TEI interrupt request is enabled.
R/W