Datasheet

Section 19 Watchdog Timer (WDT)
REJ09B0465-0300 Rev. 3.00 Page 673 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
19.3.2 Watchdog Timer Setting Flow
The watchdog timer should be set using the procedure shown in figure 19.3.
Reset released
After reset is released, the WDT starts counting
with φloco/8.
End
[1]
Clear TMWI in TCSRWD to 0.
Set TMWD to H'F1
Set TMWD to H'FE
Set TMWDto H'F7
Set TMWD to H'F8
Set TMWI in TCSRWD to 1.
TMWLOCK in TCSRWD 1.
Clear B4WI to 0 and set
TCSRWE to 1 in TCSRWD.
[2]
[3]
Y
Y
Y
N
N
N
[4]
[5]
[6]
[7]
[8]
Is WDT used?
Is clock source
changed?
Is TMWD locked down?
[1] Release the WDT from module
standby .
[2][3]Set TMWD to write-enable.
[4][5]The clock source is changed. In this
flowchart, the clock is changed to
φloco/32. In [4], the set value is
continuously written to with the MOV
instruction. In [5], the bit-set value is
bit-inverted and written.
[6][7]When the watchdog timer is not used,
clock input is set to be disabled. In [6],
the set value is continuously written to
with the MOV instruction. In [7], the bit-
set value is bit-inverted and written.
[8] After TMWD is written to, the TMWI bit
in TCSRWD is automatically set to 1.
[9] To lock down TMWD, set the
TMWLOCK bit in TCSRWD to 1.
Clear MSTWDT in MSTCR1 to 0.
[9]
Figure 19.3 Watchdog Timer Setting Flow