Datasheet

Section 19 Watchdog Timer (WDT)
REJ09B0465-0300 Rev. 3.00 Page 669 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
19.2.3 Timer Mode Register WD (TMWD)
Address:
Bit:
Value after reset:
b7
⎯
1
b6
⎯
1
b5
⎯
1
b4
⎯
1
b3
0
b2
0
b1
0
b0
0
H'FFFF99
CKS[3:0]
Bit Symbol Bit Name Description R/W
7 to 4 ⎯ Reserved These bits are read as 1. The write value should
always be 1.
⎯
3 to 0 CKS[3:0] Clock select 0000: Internal clock: counts on φloco/8 (initial value)
0001: Internal clock: counts on φloco/32
0010: Internal clock: counts on φloco/128
0011: Internal clock: counts on φloco/512
0100: Internal clock: counts on φloco/1024
0101: Internal clock: counts on sub/4
0110: Internal clock: counts on φsub/256
0111: Clock input prohibited.
1000: Internal clock: counts on φ/64
1001: Internal clock: counts on φ/128
1010: Internal clock: counts on φ/256
1011: Internal clock: counts on φ/512
1100: Internal clock: counts on φ/1024
1101: Internal clock: counts on φ/2048
1110: Internal clock: counts on φ/4096
1111: Internal clock: counts on φ8192
R/W
Note: Only write values to this register while the bus master operation clock φs is not being
frequency-divided (the value of the PHIS[2:0] bits in LPCR3 is B'000).
• CKS[3:0] bits (clock select)
The method by which this register is written differs from other registers. The register must be
written by using the MOV instruction twice in succession. First, write the data to be loaded to
TMWD in a first operation, then write a bit reversal value of the data (b3 to b0) to be loaded in
a second operation. When correct operation is executed, CKS[3:0] bits are rewritten after the
second write. If the first data and the second reversal data do not match, all bits are not
modified. Set CKS[3:0] bits to B'0111 (clock input prohibited) to stop WDT operation.