Datasheet

Section 19 Watchdog Timer (WDT)
Page 668 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Bit Symbol Bit Name Description R/W
3 TMWLOCK Timer mode
register WD
lockdown
The TMWD register is write-protected when this bit is 1.
Once this bit is set to 1, this bit can be cleared only by a
reset.
0: Writing to the TMWD register is enabled.
1: Writing to the TMWD register is disabled.
[Setting condition]
• When 1 is written to this bit
[Clearing condition]
• Resetting
R/W
2 TMWI Timer mode
register WD
write inhibit
0: Writing to the TMWD register is enabled.
1: Writing to the TMWD register is disabled.
[Setting conditions]
• This bit is automatically set to 1 after TMWD is written
to.
• When 1 is written to this bit.
[Clearing condition]
• When 0 is written to TMWI while TCSRWE is 1
R/W
1, 0 ⎯ Reserved These bits are read as 1. The write value should always
be 1.
⎯
Note: TCSRWD must be rewritten by using the MOV instruction. The bit manipulation instruction
cannot be used to change the setting value.
19.2.2 Timer Counter WD (TCWD)
Address:
Bit:
Value after reset:
b7
0
b6
0
b5
0
b4
0
b3
0
b2
0
b1
0
b0
0
H'FFFF98
TCWD is an 8-bit readable/writable up-counter. When TCWD overflows from H'FF to H'00, the
internal reset signal is generated. TCWD is initialized to H'00. TCWD can also be used as a
periodic timer. It issues an interrupt request to the CPU when the upper two bits in TCWD are
B'01, B'10, or B'11 according to the TICRWD setting.