Datasheet

Section 19 Watchdog Timer (WDT)
REJ09B0465-0300 Rev. 3.00 Page 667 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
19.2 Register Descriptions
The watchdog timer has the following registers.
• Timer control/status register WD (TCSRWD)
• Timer counter WD (TCWD)
• Timer mode register WD (TMWD)
• Timer interrupt control register WD (TICRWD)
• Timer interrupt flag register WD (TIFRWD)
19.2.1 Timer Control/Status Register WD (TCSRWD)
Address:
Bit:
Value after reset:
b7
B6WI
1
b6
TCWE
0
b5
B4WI
1
b4
TCSRWE
0
b3
TMWLOCK
0
b2
TMWI
1
b1
⎯
1
b0
⎯
1
H'FFFF9A
Bit Symbol Bit Name Description R/W
7 B6WI Bit 6 write
inhibit
0: Writing to the TCWE bit (bit 6 in this register) is
enabled.
1: Writing to the TCWE bit (bit 6 in this register) is
disabled.
This bit is always read as 1.
R/W
6 TCWE Timer counter
WD write
enable
0: Writing to the TCWD register is disabled.
1: Writing to the TCWD register is enabled.
Before writing data to this bit, the B6WI bit must be
cleared to 0.
R/W
5 B4WI Bit 4 write
inhibit
0: Writing to the TCSRWE bit (bit 4) is enabled.
1: Writing to the TCSRWE bit (bit 4) is disabled.
This bit is always read as 1.
R/W
4 TCSRWE Timer
control/status
register WD
write enable
0: Writing to TMWLOCK and TMWI (bits 3 and 2 in this
register) is disabled.
1: 0: Writing to TMWLOCK and TMWI (bits 3 and 2 in this
register) is enabled.
Before writing data to this bit, the B4WI bit must be
cleared to 0.
R/W