Datasheet

Section 19 Watchdog Timer (WDT)
Page 666 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
19.1 Features
• Selectable from fifteen clock sources
⎯ Eight clocks generated by dividing φ: φ/64, φ/128, φ/256, φ/512, φ/1024, φ/2048, φ/4096,
and φ/8192
⎯ Five clocks generated by dividing low-speed OCO clock: φloco/8, φloco/32, φloco/128,
φloco/512, and φloco/1024
⎯ Two clocks generated by dividing subclock: φsub/4 and φsub/256
When the low-speed OCO clock or subclock is selected, the WDT operates as the watchdog
timer in any operating mode.
• Reset signal generated on counter overflow
An overflow period of 1 to 256 times the selected clock can be set.
• The watchdog timer is enabled in the initial state.
The watchdog timer starts operating after a reset is released.
• Periodic timer function
The timer counter can also be used as a periodic timer. Interrupts can be generated with a
specific count value.