Datasheet

Section 18 Timer RG
Page 660 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
(3) Note on Phase Counting Mode
In phase counting mode, the phase difference and overlap between TCLKA and TCLKB must be
at least 1.5 × φ cycle of the system clock when bits TPSC2 to TPSC0 in TRGCR = B'0XX or
B'100, and the pulse width must be at least 3 × φ cycle. Figure 18.17 shows the input clock
conditions in phase counting mode.
Phase
difference
Overlap Overlap
Phase
difference
Pulse
width
Pulse
width
TCLKA
TCLKB
Phase difference and overlap: 1.5 states or more
Pulse width: 3 states or more
Figure 18.17 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode
Note: When CNTEN7 to CNTEN0 in TRGCNTCR are cleared, the counting is not performed
even if an increment/decrement condition matches.
18.3.4 Buffer Operation
Buffer operation differs according to whether GR has been designated as an output compare
register or an input capture register.
Table 18.10 shows the register combinations used in buffer operation.
Table 18.10 Register Combinations in Buffer Operation
General Register Buffer Register
GRA BRA
GRB BRB