Datasheet

Section 18 Timer RG
REJ09B0465-0300 Rev. 3.00 Page 649 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
(b) Example of input capture operation
Figure 18.7 shows an example of input capture operation.
In this example both rising and falling edges have been selected as the TGIOA pin input capture
input edge, falling edge has been selected as the TGIOB pin input capture input edge, and counter
clearing by GRB input capture has been designated for TRGCNT.
H'0160
H'0180
H'0000
H'0005
TGIOB
Time
TRGCNT value
TGIOA
GRA
GRB
H'0005
H'0180
H'0160
Figure 18.7 Example of Input Capture Operation
(c) Input capture signal timing
Rising edge, falling edge, or both edges can be selected as the detection edge for input capture
with TRGIOR.
Figure 18.8 shows input capture signal timing when the falling edge has been selected.
The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at
least 2.5 states in the case of both-edge detection.