Datasheet

Section 18 Timer RG
Page 640 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
18.2.7 Timer RG Counter (TRGCNT)
H'FF0640
b15
0
b14
0
b13
0
b12
0
b11
0
b10
0
b9
0
b8
0
b7
0
b6
0
b5
0
b4
0
b3
0
b2
0
b1
0
b0
0
Address:
Bit:
Value after reset:
TRGCNT is a 16-bit readable/writable register that performs count operation with an input clock.
The input clock is selected by bits TPSC2 to TPSC0 in TRGCR.
TRGCNT is incremented or decremented in phase counting mode and is only incremented in other
modes.
TRGCNT can be cleared to H'0000 by a compare match with the relevant GRA or GRB or by an
input capture to GRA or GRB (counter clearing function).
When TRGCNT overflows (changes from H'FFFF to H'0000), the OVF flag in TRGSR is set to 1.
When TRGCNT underflows (changes from H'0000 to H'FFFF), the UDF flag in TRGSR is set to
1.
TRGCNT must always be read from or written to in units of 16 bits; 8-bit accesses are not
allowed. TRGCNT is initialized to H'0000 by a reset.