Datasheet

Section 18 Timer RG
REJ09B0465-0300 Rev. 3.00 Page 639 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Bit Symbol Bit Name Description R/W
0 IMFA Input capture/
compare
match flag A
[Setting conditions]
• TRGCNT = GRA when GRA functions as an output
compare register
• The TRGCNT value is transferred to GRA by an input
capture signal when GRA functions as an input
capture register
[Clearing condition]
• When the DTC is activated by an IMFA interrupt, and
the DISEL bit in MRB of the DTC is 0.
• When IMFA is read when IMFA = 1, then 0 is written
to.
R/W
18.2.6 Timer RG Interrupt Enable Register (TRGIER)
TRGIER is a register that controls interrupt requests of timer RG.
Address:
Bit:
Value after reset:
b7
⎯
1
b6
⎯
1
b5
⎯
1
b4
⎯
1
b3
OVIE
0
b2
UDIE
0
b1
IMIEB
0
b0
IMIEA
0
H'FF064B
Bit Symbol Bit Name Description R/W
7 to 4 ⎯ Reserved These bits are read as 1. The write value should
always be 1.
⎯
3 OVIE Overflow interrupt
enable
0: Interrupt by the OVF flag is disabled.
1: Interrupt by the OVF flag is enabled.
R/W
2 UDIE Underflow interrupt
enable
0: Interrupt by the UDF flag is disabled.
1: Interrupt by the UDF flag is enabled.
R/W
1 IMIEB Input capture/
compare match B
enable
0: Interrupt by the IMFB flag is disabled.
1: Interrupt by the IMFB flag is enabled.
R/W
0 IMIEA Input capture/
compare match A
enable
0: Interrupt by the IMFA flag is disabled.
1: Interrupt by the IMFA flag is enabled.
R/W