Datasheet

Section 18 Timer RG
Page 638 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
18.2.5 Timer RG Status Register (TRGSR)
Address:
Bit:
Value after reset:
b7
1
b6
1
b5
1
b4
DIRF
0
b3
OVF
0
b2
UDF
0
b1
IMFB
0
b0
IMFA
0
H'FF064A
Bit Symbol Bit Name Description R/W
7 to 5 Reserved These bits are read as 1. The write value should be 1.
4 DIRF Count
direction flag
0: TRGCNT is decremented.
1: TRGCNT is incremented.
R
3 OVF Overflow flag [Setting condition]
When TRGCNT overflows from H'FFFF to H'0000
[Clearing condition]
When OVF is read when OVF = 1, then 0 is written to.
R/W
2 UDF Underflow flag [Setting condition]
When TRGCNT underflows from H'0000 to H'FFFF
[Clearing condition]
When UDF is read when UDF = 1, then 0 is written to.
UDF is valid when phase counting mode is used (MDF in
TRGMDR is 1).
R/W
1 IMFB Input capture/
compare
match flag B
[Setting conditions]
TRGCNT = GRB when GRB functions as an output
compare register
The TRGCNT value is transferred to GRB by an input
capture signal when GRB functions as an input
capture register
[Clearing condition]
When the DTC is activated by a IMFB interrupt, and
the DISEL bit in MRB of the DTC is 0.
When IMFB is read when IMFB = 1, then 0 is written
to.
R/W