Datasheet

Section 18 Timer RG
REJ09B0465-0300 Rev. 3.00 Page 635 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
18.2.3 Timer RG Control Register (TRGCR)
Address:
Bit:
Value after reset:
b7
⎯
1
b6
0
b5
0
b4
0
b3
0
b2
0
b1
TPSC[2:0]
0
b0
0
H'FF0648
CCLR[1:0] CKEG[1:0]
Bit Symbol Bit Name Description R/W
7 ⎯ Reserved This bit is read as 1. The write value should be 1. ⎯
6, 5 CCLR[1:0] Counter clear
source select
00: Disables clearing TRGCNT.
01: Clears TRGCNT with a GRA compare match/input
capture.
1X: Clears TRGCNT with a GRB compare match/input
capture.
R/W
4, 3 CKEG[1:0] External clock
detection edge
select
00: Incremented at the rising edges.
01: Incremented at the falling edges.
1x: Incremented at the rising and falling edges.
R/W
2 to 0 TPSC[2:0] TRGCNT count
clock select
000: TRGCNT counts the internal clock φ
001: TRGCNT counts the internal clock φ/2
010: TRGCNT counts the internal clock φ/4
011: TRGCNT counts the internal clock φ/8
100: TRGCNT counts the internal clock φ/32
101: TRGCNT counts the TCLKA pin input
110: Setting prohibited
111: TRGCNT counts the TCLKB pin input
R/W
[Legend]
X: Don't care.
• CKEG[1:0] bits (external clock detection edge select)
Selects an edge of the external clock to be detected. When phase counting mode is used, the
phase counting operation is performed regardless of the CKEG[1:0] setting.
• TPSC[2:0] bits (TRGCNT count clock select)
The settings are invalid in phase counting mode.