Datasheet

Section 18 Timer RG
Page 634 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
• MDF bit (Phase counting mode select)
When this bit is 0, the counter counts the clock pulses specified with the TPSC2 to TPSC0 bits
in TRGCR. When this bit is 1, the counter counts the phases produced by TCLKA and
TCLKB as specified in TRGCNTCR.
18.2.2 Timer RG Counter Control Register (TRGCNTCR)
Address:
Bit:
Value after reset:
b7
CNTEN7
0
b6
CNTEN6
0
b5
CNTEN5
0
b4
CNTEN4
0
b3
CNTEN3
0
b2
CNTEN2
0
b1
CNTEN1
0
b0
CNTEN0
0
H'FF0647
Bit Symbol Bit Name Description R/W
7 CNTEN7 Count enable
bit 7
0: Not affected by the TCLKB rising edge when TCLKA is low.
1: Incremented at the TCLKB rising edge when TCLKA is low.
R/W
6 CNTEN6 Count enable
bit 6
0: Not affected by the TCLKA rising edge when TCLKB is high.
1: Incremented at the TCLKA rising edge when TCLKB is high.
R/W
5 CNTEN5 Count enable
bit 5
0: Not affected by the TCLKB falling edge when TCLKA is high.
1: Incremented at the TCLKB falling edge when TCLKA is high.
R/W
4 CNTEN4 Count enable
bit 4
0: Not affected by the TCLKA falling edge when TCLKB is low.
1: Incremented at the TCLKA falling edge when TCLKB is low.
R/W
3 CNTEN3 Count enable
bit 3
0: Not affected by the TCLKA falling edge when TCLKB is high.
1: Incremented at the TCLKA falling edge when TCLKB is high.
R/W
2 CNTEN2 Count enable
bit 2
0: Not affected by the TCLKB falling edge when TCLKA is low.
1: Incremented at the TCLKB falling edge when TCLKA is low.
R/W
1 CNTEN1 Count enable
bit 1
0: Not affected by the TCLKA rising edge when TCLKB is low.
1: Incremented at the TCLKA rising edge when TCLKB is low.
R/W
0 CNTEN0 Count enable
bit 0
0: Not affected by the TCLKB rising edge when TCLKA is high.
1: Incremented at the TCLKB rising edge when TCLKA is high.
R/W