Datasheet

Section 18 Timer RG
REJ09B0465-0300 Rev. 3.00 Page 633 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
18.2.1 Timer RG Mode Register (TRGMDR)
Address:
Bit:
Value after reset:
b7
STR
0
b6
⎯
1
b5
0
b4
0
b3
DFB
0
b2
DFA
0
b1
MDF
0
b0
PWM
0
H'FF0646
DFCK[1:0]
Bit Symbol Bit Name Description R/W
7 STR Counter start 0: TRGCNT stops counting.
1: TRGCNT performs counting.
R/W
6 ⎯ Reserved This bit is read as 1. The write value should be 1. ⎯
5, 4 DFCK[1:0] Digital filter
clock select
00: φ/32 (initial value)
01: φ/8
10: φ
11: φ/32Clock specified by bits CKS2 to CKS0 in TRGCR
R/W
3 DFB TGIOB pin
digital filter
function select
0: Disables the digital filter for the TGIOB pin.
1: Enables the digital filter for the TGIOB pin.
R/W
2 DFA TGIOB pin
digital filter
function select
0: Disables the digital filter for the TGIOA pin.
1: Enables the digital filter for the TGIOA pin.
R/W
1 MDF Phase
counting mode
select
0: Increments the counter.*
1
1: Phase counting mode
R/W
0 PWM PWM mode
select
0: Usual mode*
2
1: PWM mode
R/W
Notes: 1. Select counting up in PWM mode.
2. Select normal mode here when the MDF bit is set for phase counting mode.
• STR bit (Counter start)
Clearing this bit to 0 stops counting by TRGCNT. Counting by TRGCNT proceeds while this
bit is set to 1.
This bit is set to 1 if the specified event occurs when operation of timer RG has been selected
in ELOPC of the event link controller.