Datasheet

Section 18 Timer RG
REJ09B0465-0300 Rev. 3.00 Page 631 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Internal clock
External clock TCLKA
TCLKB
φ/2
φ/4
φ/8
φ/32
TGIOA
TGIOB
OVFG
Control logic
Clock selection
Comparator
UDFG
IMFAG
IMFBG
TRGCNT
Internal data bus
Bus interface
GRA GRB
BRA BRB
TRGMDR
TRGCNTCR
TRGCR
TRGIOR
TRGSR
TRGIER
Module data bus
I/O pin
Interrupt request
Figure 18.1 Timer RG Block Diagram
Table 18.2 summarizes the timer RG pins.
Table 18.2 Pin Configuration
Pin Name I/O Function
TCLKA Input External clock A input pin (Phase A input pin in phase
counting mode)
TCLKB Input External clock B input pin (Phase B input pin in phase
counting mode)
TGIOA I/O GRA output compare output pin/
GRA input capture input pin/
PWM output pin in PWM mode
TGIOB I/O GRB output compare output pin/
GRB input capture input pin