Datasheet

Section 17 Timer RE
Page 624 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Internal data bus
TREO pin
φ/2
φ/4
φ/8
φ/32
φsub
Output
control
circuit
1/4
1/2
4-bit
counter
8-bit
counter
Comparison
circuit
Interrupt
control
circuit
TREMINTRESEC
Interrupt
request
RCS2
Match signal
[Legend]
TRESEC: Timer RE second data register/counter data register
TREMIN: Timer RE minute data register/compare data register
RCS2 to RCS0: Bits 2 to 0 in TRECSR
RCS[1:0]
Figure 17.6 Block Diagram of Output Compare Mode