Datasheet

Section 17 Timer RE
Page 618 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
17.2.8 Timer RE Clock Source Select Register (TRECSR)
Address:
Bit:
Value after reset:
b7
⎯
0
b6
0
b5
RCS[6:4]
0
b4
0
b3
RCS3
1
b2
RCS2
0
b1
0
b0
0
H'FFFFAF
RCS[1:0]
Bit Symbol Bit Name Description R/W
7 ⎯ Reserved This bit is read as 0. The write value should be 0. ⎯
6 to 4 RCS[6:4]*
2
Clock output
select
000: φ/2
001: φ/4
010: φ/8
011: Compare-match output (Only valid in output-
compare mode)
100: φ/sub (32.768 kHz)
101: 1 Hz (Only valid in realtime clock mode)
11x: Setting prohibited
R/W
3 RCS3 Mode select
0: Output-compare mode
1: Realtime clock mode
R/W
2 RCS2 4-bit counter
select
(Only valid in output-compare mode)
0: Does not use the 4-bit counter.
1: Uses the 4-bit counter.
R/W
1, 0 RCS[1:0]
*
1
*
3
Clock source
select
00: φ/2
01: φ/4
10: φ/8
11: φ/sub
R/W
[Legend]
X: Don't care
Notes: 1. RCS[1:0] should be set when realtime clock mode is used or when counter operation is
stopped.
2. RCS[6:4] should be set when the TOENA bit in TRECR1 is 0.
3. In output compare mode, when the CPU is in a φloco clock mode, do not select the
φsub clock as the clock source for the timer.