Datasheet

Section 17 Timer RE
Page 616 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
17.2.7 Timer RE Interrupt Flag Register (TREIFR)
Address:
Bit:
Value after reset:
b7
⎯
0
b6
⎯
0
b5
COMF
0
b4
WKF
0
b3
DYF
0
b2
HRF
0
b1
MNF
0
b0
SECF
0
H'FFFFAE
Bit Symbol Bit Name Description R/W
7, 6 ⎯ Reserved These bits are read as 0. The write value should be 0. ⎯
5 COMF Compare-
match
interrupt
request flag
[Setting condition]
• When the counter value matches the value set in
TREMIN in output-compare mode.
[Clearing condition]
• When 1 is read from the bit and then 0 is written to
the bit.
R/W
4 WKF Week periodic
interrupt
request flag
[Setting condition]
• When bits WK[2:0] in TREWK reach B’000 in realtime
clock mode.
[Clearing condition]
• When 1 is read from the bit and then 0 is written to
the bit.
When the DTC is activated with a week periodic interrupt
and the DISEL bit in the MRB register of the DTC is 1.
R/W
3 DYF Day periodic
interrupt
request flag
[Setting condition]
• Each time TREWK is updated in realtime clock mode.
(Occurs every day)
[Clearing conditions]
• When 1 is read from the bit and then 0 is written to
the bit.
• When the DTC is activated with a day periodic
interrupt and the DISEL bit in the MRB register of the
DTC is 1.
R/W