Datasheet

Section 17 Timer RE
Page 614 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
• Output-compare mode
Bit Symbol Bit Name Description R/W
7 TSTART Counter
operation start
0: Stops timer counter operation.
1: Starts timer counter operation.
R/W
6 H12_H24 Operating mode 0 should be written to this bit in output-compare mode. R/W
5 PM a.m./p.m.
0 should be written to this bit in output-compare mode.
R/W
4 TRESET Reset
0: Normal operation
1: Resets all the registers and control circuits, except
TRECSR and the TOENA and TRESET bits in this
register. Clear this bit to 0 after having been set to 1.
R/W
3 INT Interrupt
generation
timing
0 should be written to this bit in output-compare mode. R/W
2 TOENA TREO pin
output enable
0: Disables timer RE divided clock output.
1: Enables timer RE divided clock output.
R/W
1 TCSTF Operation status
flag
0: Indicates that timer RE operation has been stopped.
1: Indicates that timer RE operation is in progress.
R
0 ⎯ Reserved This bit is read as 0. The write value should be 0. ⎯
Note: After writing 1 to TSTART, the timer RE should not be accessed before reading 1 from
TCSTF, with the exception of reading TCSTF. Similarly, after writing 0 to TSTART, the timer
RE should not be accessed before reading 0 from TCSTF, with the exception of reading
TCSTF.