Datasheet

Section 17 Timer RE
Page 612 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
17.2.5 Timer RE Control Register 1 (TRECR1)
Address:
Bit:
Value after reset:
b7
TSTART
⎯
b6
H12_H24
⎯
b5
PM
⎯
b4
TRERST
0
b3
INT
0
b2
TOENA
0
b1
TCSTF
⎯
b0
⎯
0
H'FFFFAC
• Realtime clock mode
Bit Symbol Bit Name Description R/W
7 TSTART Counter
operation start
0: Stops timer counter operation
1: Starts timer counter operation
R/W
6 H12_H24*
1
Operating
mode
0: The timer RE operates in 12-hour mode. TREHR
counts on 0 to 11.
1: The timer RE operates in 24-hour mode. TREHR
counts on 0 to 23.
R/W
5 PM*
1
a.m./p.m.
0: Indicates a.m. when the timer RE is in the 12-hour
mode.
1: Indicates p.m. when the timer RE is in the 12-hour
mode.
R/W
4 TRESET Reset
0: Normal operation
1: Resets all the registers and control circuits, except
TRECSR and the TOENA and TRESET bits in this
register. Clear this bit to 0 after having been set to 1.
R/W
3 INT*
1
Interrupt
generation
timing
0: Generates a second, minute, hour, or day-of-week
periodic interrupt during timer RE busy period.
1: Generates a second, minute, hour, or day-of-week
periodic interrupt immediately after completing timer
RE busy period.*
2
R/W
2 TOENA TREO pin
output enable
0: Disables timer RE divided clock output.
1: Enables timer RE divided clock output.
R/W
1 TCSTF Operation
status flag
0: Indicates that timer RE operation has been stopped.
1: Indicates that timer RE operation is in progress.
R
0 ⎯ Reserved This bit is read as 0. The write value should be 0. ⎯
Notes: 1. Bits H12_H24, PM, and INT should be set when the timer RE operation is stopped.
2. This bit should be set to 1 in realtime clock mode and cleared to 0 in output compare
mode.