Datasheet

Section 2 CPU
REJ09B0465-0300 Rev. 3.00 Page 37 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Bit Symbol Bit Name Description R/W
2 Z Zero flag [Setting condition]
When data is zero.
[Clearing condition]
When data is not zero.
R/W
1 V Overflow flag [Setting condition]
When an overflow occurs after an arithmetic
instruction has been executed.
[Clearing condition]
When no overflow occurs after an arithmetic
instruction has been executed.
R/W
0 C Carry flag [Setting condition]
When a carry occurs after an instruction has been
executed.
[Clearing condition]
When no carry occurs after an instruction has been
executed.
R/W
• I (interrupt mask bit)
This bit masks interrupts other than NMI when set to 1. NMI is accepted regardless of the I bit
setting. The I bit is set to 1 at the start of an exception-handling sequence. For details, see
section 4, Interrupt Controller.
• UI (user bit/interrupt mask bit)
This bit can be written to and read from by software using the LDC, STC, ANDC, ORC, and
XORC instructions.
For this LSI, interrupt mask bit is not available.
• H (half carry flag)
When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B or NEG.B instruction is executed, this
flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the
ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is
a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or
NEG.L instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 27, and
cleared to 0 otherwise.