Datasheet

Section 16 Timer RD
REJ09B0465-0300 Rev. 3.00 Page 601 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
(7) Conflict between Count Clearing and Increment Operations by Input Capture
If an input capture and increment signals are simultaneously generated, count clearing by the input
capture operation has priority without an increment operation. The TRDCNT contents before
clearing counter are transferred to GR. Figure 16.71 shows the timing in this case.
TRDCNT
Input capture
signal
Counter clear
signal
TRDCNT input
clock
Clearing has priority.
N
H'0000
GR
N
φ
Figure 16.71 Conflict between Count Clearing and Increment Operations
by Input Capture