Datasheet

Section 16 Timer RD
Page 600 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
(6) Conflict between GR Read and Input Capture
If an input capture signal is generated in the T
2
state of a GR read cycle, the data that is read will
be transferred before input capture transfer. Figure 16.70 shows the timing in this case.
φ
GR address
GR read cycle
GR
X
X
M
T
1 T 2
Input capture
signal
Internal read
signal
Internal
data bus
Figure 16.70 Conflict between GR Read and Input Capture