Datasheet

Section 16 Timer RD
Page 598 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
(4) Conflict between GR Write and Compare Match
If a compare match occurs in the T
2
state of a GR write cycle, GR write has priority and the
compare match signal is disabled. Figure 16.68 shows the timing in this case.
φ
WGR
(internal write signal)
GR address
GR write cycle
GR
Compare match
signal
N
M
T
1 T 2
GR write data
Disabled
TRDCNT
N
N+1
Figure 16.68 Conflict between GR Write and Compare Match