Datasheet

Section 16 Timer RD
REJ09B0465-0300 Rev. 3.00 Page 597 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
(2) Conflict between TRDCNT Write and Clear Operations
If a counter clear signal is generated in the T
2
state of a TRDCNT write cycle, TRDCNT clearing
has priority and the TRDCNT write is not performed. Figure 16.66 shows the timing in this case.
φ
WTRDCNT
(internal write signal)
TRDCNT address
TRDCNT write cycle
Clearing has priority.
TRDCNT
N
H'0000
T
1 T2
Counter clear signal
Figure 16.66 Conflict between TRDCNT Write and Clear Operations
(3) Conflict between TRDCNT Write and Increment Operations
If TRDCNT is incremented in the T
2
state of a TRDCNT write cycle, writing has priority. Figure
16.67 shows the timing in this case.
φ
WTRDCNT
(internal write signal)
TRDCNT address
TRDCNT write cycle
TRDCNT N
M
T
1 T 2
TRDCNT input clock
TRDCNT write data
Figure 16.67 Conflict between TRDCNT Write and Increment Operations