Datasheet

Section 16 Timer RD
Page 596 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
16.4.2 Status Flag Clearing Timing
The status flag can be cleared by writing 0 after reading 1 from the CPU. Figure 16.65 shows the
timing in this case.
φ
IMF, OVF
WTRDSR
Address
(internal write signal)
TRDSR address
Figure 16.65 Status Flag Clearing Timing
16.5 Usage Notes
(1) Input Pulse Width of Input Clock Signal and Input Capture Signal
When the digital filtering function for input is not in use, the pulse width of the input clock signal
and the input capture signal must be at least three system clock (φ) cycles when the TPSC2 to
TPSC0 bits in TRDCR = B'0XX or B'10X; shorter pulses will not be detected correctly.