Datasheet

Section 2 CPU
Page 36 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
2.4.4 Condition-Code Register (CCR)
This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and
half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags.
Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC
instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch
(Bcc) instructions.
Bit Symbol Bit Name Description R/W
7 I Interrupt mask
bit
0: Does not mask interrupts.
1: Masks interrupts.
R/W
6 UI User bit or
interrupt mask
bit
This bit does not affect this LSI operation. R/W
5 H Half-carry flag [Setting conditions]
• If there is a carry or borrow bit 3 when the
ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B or
NEG.B instruction is executed.
• If there is a carry or borrow at bit 11 when the
ADD.W, SUB.W, CMP.W, or NEG.W instruction
is executed.
• If there is a carry or borrow at bit 27 when the
ADD.L, SUB.L, CMP.L, or NEG.L instruction is
executed.
[Clearing condition]
When none of the above setting conditions are
satisfied.
R/W
4 U User bit This bit does not affect the LSI operation. R/W
3 N Negative flag [Setting condition]
When the execution result is negative.
[Clearing condition]
When the execution result is not negative.
R/W