Datasheet

Section 16 Timer RD
Page 590 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Figure 16.56 is an example when non-overlapped pulses are output on pins FTIOA0 and FTIOB0.
In this example, TRDCNT_0 functions as a periodic counter which is cleared on compare match
A0 (bits CCLR2 to CCLR0 in TRDCR_0 are set to B'001), an output signal is toggled on compare
match A (bits IOA2 to IOA0 in TRDIORA_1 are set to B'011), the output signal on the FTIOA
pin is toggled on compare match C (GRC_0) (bits IOC3 to IOC0 in TRDIORC_1 are set to
B'0X11), an output signal is toggled on compare match B (GRB_0) (bits IOB2 to IOB0 in
TRDIORA_1 are set to B'011), and the output signal on the FTIOB pin is toggled on compare
match D (GRD_0) (bits IOD3 to IOD0 in TRDIORC_1 are set to B'0X11). The cycle of the pulse
is arbitrary.
Similarly, figure 16.57 is an example when non-overlapped pulses are output using TRDCNT_1.
H'FFFF
H'0000
GRA_0
GRC_0
GRB_0
GRD_0
FTIOA0
FTIOB0
TRDCNT value
Counter cleared on GRA_0
compare match
Time
Figure 16.56 Example of Non-Overlapped Pulses Output on Pins FTIOA0 and FTIOB0
(TRDCNT_0 Used)
TRDCNT value
H'FFFF
H'0000
GRA_1
GRC_1
GRB_1
GRD_1
FTIOA1
FTIOB1
Counter cleared on GRA_1
compare match
Time
Figure 16.57 Example of Non-Overlapped Pulses Output on Pins FTIOA1 and FTIOB1
(TRDCNT_1 Used)