Datasheet

Section 16 Timer RD
Page 588 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
16.3.11 Digital Filtering Function for Input Capture Inputs
Input signals on the FTIOA to FTIOD pins can be input via the digital filters. The digital filter
includes three latches connected in series and a match detector circuit. The latches operate on the
sampling clock specified by bits DFCK1 and DFCK0 in TRDDF and stores an input signal on the
FTIOA to FTIOD pins. When outputs of the three latches match, the match detector circuit outputs
the signal level of the input. Otherwise, the output remains unchanged. That is, when a pulse width
is equal to or greater than three sampling clock cycles, the pulse is input as a signal. When a pulse
width is less than three sampling clock cycles, the pulse is considered as a noise to be removed.
FTIOA0 (TCLK)
φ/32
φ/8
φ/4
φ/2
φ
FTIOA to FTIOD
input signals
Cycle of a clock specified by
TPSC2 to TPSC0 or DFCK1
and DFCK0
Signal change is not output unless
signal levels match three times.
Signal propagation delay:
5 sampling clocks
TPSC2 to
TPSC0
DFCK1 and
DFCK0
DFA to DFD
IOA1, IOA0,
IOD1, and IOD0
Sampling clock
φ/32
φ/8
φ
Match
detector
circuit
Selecter
Edge
detecting
circuit
Sampling clock
C
Latch
DQ
C
Latch
DQ
C
Latch
D
Q
Digital-filtered signal
φ
C
Latch
Q
C
Latch
Q
D
D
FTIOA to FTIOD
Figure 16.54 Block Diagram of Digital Filter