Datasheet

Section 16 Timer RD
REJ09B0465-0300 Rev. 3.00 Page 585 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
16.3.10 Timer RD Output Timing
The outputs of channels 0 and 1 can be disabled or inverted by the settings of TRDOER1 and
TRDOCR and the external level.
(1) Output Disable/Enable Timing of Timer RD by TRDOER1
Setting the master enable bit in TRDOER1 to 1 disables the output of timer RD. By setting the
PCR and PDR of the corresponding I/O port beforehand, any value can be output. Figure 16.50
shows the timing to enable or disable the output of timer RD by TRDOER1.
φ
Timer RD
output pin
Address bus
TRDOER1 address
I/O port
Timer RD output
I/O port
TRDOER1 0
1
T
1 T2
Timer output
Figure 16.50 Example of Output Disable Timing of Timer RD by Writing to TRDOER1